1. Field of the Invention
The present invention relates to a Low Drop-Out (LDO) regulator, and more particularly, to an LDO regulator with fast current limit.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional LDO regulator 100. As shown in FIG. 1, the LDO regulator 100 comprises a sensing resistor RSEN, a reference resistor RREF, two feedback resistors RFB1 and RFB2, a reference current source IREF, a comparator CMP, an error amplifier EA, and a transistor Q1. The transistor Q1 is a P channel Metal Oxide Semiconductor (PMOS) transistor.
The LDO regulator 100 is used to convert an input voltage source VIN to an output voltage source VOUT for providing the voltage VOUT and the load current ILOAD to the load X. The detail of operation principles is explained as follows.
The feedback resistors RFB1 and RFB2 are coupled between the output voltage source VOUT and a ground end for providing a feedback voltage VFB divided from the output voltage VOUT to the error amplifier EA. The error amplifier EA comprises a positive input end for receiving the feedback voltage VFB, a negative input end for receiving a reference voltage VREF2, and an output end for outputting a current control signal VA according to the signals received on the positive and negative input ends of the error amplifier EA. The control end (gate) of the transistor Q1 is coupled to the output end of the error amplifier EA for receiving the current control signal VA. In this way, the transistor Q1 controls the magnitudes of the output voltage VOUT and the load current ILOAD according to the current control signal VA. More particularly, if the voltage of the current control signal VA is lower, the load current ILOAD is higher; if the voltage of the current control signal VA is lower, the load current ILOAD is higher. Consequently, when the feedback voltage VFB is lower than the reference voltage VREF2 (for example, when the load current ILOAD drained by the load X increases), the current control signal VA generated from the error amplifier EA turns on the transistor Q1 more for raising the output voltage VOUT. That is, the voltage of the current control signal VA is decreased.
The reference resistor RREF is coupled between the input voltage source VIN, the reference current source IREF and the positive input end of the comparator CMP for providing a reference voltage VREF1 to the comparator CMP. The sensing resistor RSEN is coupled between the input voltage source VIN and the negative input end of the comparator CMP for providing the sensing voltage VSEN to the comparator CMP. The comparator CMP generates the current limit signal SC according to the comparing result of the magnitudes of the reference voltage VREF1 between the sensing voltage VSEN. More particularly, if the sensing voltage VSEN is higher than the reference voltage VREF1, the current limit signal SC is logic “0” (low voltage level); otherwise, if the sensing voltage VSEN is lower than the reference voltage VREF1, the current limit signal SC is logic “1” (high voltage level). Since the sensing resistor RSEN is serial-connected between the input voltage source VIN and the transistor Q1, the magnitude of the load current ILOAD can be detected according to the values of the sensing voltage VSEN and the sensing resistor RSEN. In this way, the load current ILOAD can be limited by the comparator CMP. More particularly, if the sensing voltage VSEN is lower than the reference voltage VREF1, which means the load current ILOAD is higher than current limit ILIMIT, the comparator CMP outputs the current limit signal with logic “1” to the error amplifier EA to disable the error amplifier EA. In other words, when the current limit signal SC is logic “1”, the error amplifier EA is disabled to keep lowering the voltage of the current control signal VA. In this way, the level of the transistor Q1 being turning on is limited, which limits the magnitude of the load current ILOAD.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating variation of the load current of the conventional LDO regulator 100. As shown in FIG. 2, the drawback of the conventional LDO regulator 100 is that, in the conventional LDO regulator 100, detecting the load current has to execute through the conversion from the sensing resistor RSEN and the comparator CMP for providing the current limit control signal SC. Therefore, by such mechanism for detecting the load current ILOAD, some reaction time has to be required in order to effectively limit the load current ILOAD. If the load current LLOAD increases excessively and suddenly (for example, the load X is short-circuited), the conventional LDO regulator 100 is not able to effectively and quickly limit the load current ILOAD so that the load current ILOAD is possibly higher than current limit ILIMIT, which damages the related components.
Additionally, since the sensing resistor RSEN and the transistor Q1 are serial-connected, consequently, the equivalent impedance between the input and the output voltage sources VIN and VOUT is increased because of the addition of the sensing resistor RSEN, causing power waste and increasing the minimal voltage difference between the input and the output voltages of the LDO regulator 100, and thus the efficiency of the LCO regulator 100 is decreased.